1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly to a structure of a novel capacitor suited for an analog circuit and to a novel manufacturing method of the same.
2. Description of Related Art
It is desirable to use a device whose bias dependency (gate bias) is small for a capacitor used in an analog circuit because it is required to operate at high speed.
FIG. 1 is a sectional view of part of a known semiconductor integrated circuit device used for an analog circuit, in which a MOS type field effect transistor (hereinafter referred to as a MOS transistor) and a two-layered poly-capacitor are formed. A field oxide film 102, i.e. a device separating region, made of LOCOS or the like is formed on the surface region of a semiconductor substrate 120 made of a P-type silicon or the like. In this known device, an N-type well region (N well) 101 is formed in the semiconductor substrate 120, a P-type MOS transistor (PMOS transistor) is formed on the device region of the N well 101 and a MOS capacitor is formed on the field oxide film 102 in the N well 101. A P+ source/drain region 117 of the two-layered poly-transistor is formed in a device region surrounded by the field oxide film 102. A gate oxide film 108 is formed on the part between the P+source/drain regions 117 by means of thermal oxidation, for example. A gate electrode is formed on the gate oxide film 108.
The gate electrode is composed of a first poly-silicon film 109 directly formed on the gate oxide film 108, a third poly-silicon film 114 formed on the first poly-silicon film 109, and a tungsten silicide film 115 formed on the third poly-silicon film 114. Meanwhile, a first electrode 119, made of a poly-silicon film, of the capacitor is formed on the field oxide film 102. Then, a silicon oxide film 121 which becomes a dielectric film is formed on the first electrode 119. A second electrode is formed on the silicon oxide film 121. The second electrode is composed of a second poly-silicon film 112 directly formed on the silicon oxide film 121, another third poly-silicon film 114 formed on the second poly-silicon film 112 and another tungsten silicide film 115 formed on the third poly-silicon film 114. A BPSG (Boron-doped Phospho-Silicate Glass) film 118 for example is coated on the semiconductor substrate 120 so as to protect the two-layered poly-capacitor and the MOS transistor. The surface of the BPSG film 118 is flattened by means of CMP (Chemical Mechanical Polishing), for example. A metal wire 122 on film is coated further on the semiconductor substrate, thus completing the semiconductor chip.
In the semiconductor integrated circuit, the voltage coefficient of the capacitor using the semiconductor substrate such as silicon as one electrode thereof is decided by a thickness of an insulating film between the capacitor electrode and the substrate and concentration of impurity implanted to the surface of the silicon substrate. The voltage coefficient degrades when the thickness is thinned and when the concentration is lowered. However, with the increase and further micronization of the integration of LSIs, it is required to thin the thickness of the gate oxide film of the MOS transistor in order to suppress a short channel effect. In the capacitor using the oxide film having the same thickness with the gate oxide film of the MOS transistor as the insulating film, the impurity concentration of the semiconductor substrate cannot exceed a solid solubility limit of the impurity within silicon and the insulation of the oxide film formed thereon also degrades when the concentration is too high, so that it is necessary to suppress the concentration to a certain degree. In such case, when positive or negative voltage is applied to the capacitor electrode, a depletion layer is formed on the silicon substrate side and the substantial thickness of the oxide film fluctuates due to the fluctuation of the applied voltage, thereby increasing the coefficient of voltage of the capacitance.
On the other hand, although an electrode such as a poly-silicon film different from the gate electrode may be used, for example, for the lower electrode of the capacitor in order to minimize the coefficient of voltage, the height of the capacitor forming region is thickened as compared to the gate electrode forming region by the thickness of the lower poly-silicon film as shown in FIG. 1 as a result. Further, it is essential to use a polishing process such as the CMP method as described above which does not involve heat treatment as the flattening technology in order to advance the micronization in the future. However, there arises a problem in such case that the upper electrode part of the capacitor, whose stepped structure differs, is exposed on the surface and the insulation with the upper aluminum wiring layer cannot be maintained as shown in FIG. 1.
Accordingly, it is an object of the present invention to solve the aforementioned problems by providing a semiconductor integrated circuit device which allows a high precision MOS capacitor to be formed without changing the performance of the MOS transistor formed on the same semiconductor substrate.
Further, it is another object of the present invention to provide a method for fabricating the semiconductor integrated circuit device which allows an interlayer insulating film formed on the MOS transistor and the capacitor to be readily flattened by equalizing the height of the MOS transistor and the capacitor to be formed on the same semiconductor substrate.
In order to solve the aforementioned problems, according to the present invention, a MOS capacitor whose coefficient of voltage is small is formed by forming a thick oxide film which is different from a gate oxide film of a MOS transistor to be formed on a same semiconductor substrate and by implanting impurity right under that by a degree without breaking the insulation. At this time, an electrode of the MOS capacitor is formed by the same layer with a gate oxide film of the MOS transistor to substantially equalize the height of both electrodes.
The high precision capacitor can be formed without changing the performance of the MOS transistor to be formed on the same semiconductor substrate. Further, an interlayer insulating film to be formed on the MOS transistor and the capacitor may be flattened readily by equalizing the height of the MOS transistor and the capacitor.
That is, according to one embodiment of the present invention, the semiconductor integrated circuit device includes a semiconductor substrate; a MOS type field effect transistor having a first silicon oxide film formed on the semiconductor substrate as a gate insulating film; and a capacitor having a second silicon oxide film formed on the semiconductor substrate as a dielectric film, a first electrode composed of the semiconductor substrate and a second electrode formed on the second silicon oxide film; where the second silicon oxide film is thicker than the first silicon oxide film.
Also, in another embodiment of the present invention, a semiconductor integrated circuit device has the semiconductor substrate; the MOS type field effect transistor having a first silicon oxide film formed on the semiconductor substrate as a gate insulating film; the capacitor having a second silicon oxide film formed on the semiconductor substrate as a dielectric film, and a first electrode composed of the semiconductor substrate and a second electrode formed on the second silicon oxide film; where the second silicon oxide film has a thickness which reduces a voltage dependency of the capacitor and which is thicker than the thickness of the first silicon oxide film.
An inventive method for fabricating a semiconductor integrated circuit device includes: forming a dummy gate oxide film on the surface of a semiconductor substrate on which a field oxide film is formed; implanting channel ion into a region of the semiconductor substrate where a MOS type field effect transistor is to be formed; forming a high concentrate impurity diffusing region by implanting impurity to a region of the semiconductor substrate where a capacitor is to be formed; forming an oxide film for a capacitor on the surface of the semiconductor substrate after peeling off the dummy gate oxide film; leaving the oxide film only in the region where the capacitor is to be formed and removing the oxide film at the region other than that; forming a gate oxide film on the surface of the semiconductor substrate; depositing a poly-silicon film including the gate oxide film on the surface of the semiconductor substrate; diffusing impurity in the poly-silicon film; depositing a conductive film on the poly-silicon film; patterning the poly-silicon film and the conductive film to form a gate electrode and a capacitor electrode at one time; and depositing an interlayer insulating film on the surface of the semiconductor substrate and then flattening the interlayer insulating film by a CMP process.
Another inventive method for fabricating a semiconductor integrated circuit device includes forming a dummy gate oxide film on the surface of a semiconductor substrate on which a field oxide film is formed; implanting channel ion into a region of the semiconductor substrate where a MOS type field effect transistor is to be formed; forming a high concentrate impurity diffusing region by implanting impurity to a region of the semiconductor substrate where a capacitor is to be formed; forming a gate oxide film on the surface of the semiconductor substrate after peeling off the dummy gate oxide film; depositing a first poly-silicon film on the semiconductor substrate; leaving the first poly-silicon film and the gate oxide film only in the region where the MOS type field effect transistor is to be formed and removing the poly-silicon film and the gate oxide film formed at the region other than that; forming a oxide film for a capacitor on the surface of the semiconductor substrate; depositing a second poly-silicon film on the semiconductor substrate; leaving the second poly-silicon film only in the region where the capacitor is to be formed and removing the second poly-silicon film formed at the region other than that; removing the capacitor oxide film formed on the first poly-silicon film; depositing a third poly-silicon film on the first and second poly-silicon films on the semiconductor substrate; diffusing impurity in the third poly-silicon film; depositing a conductive film on the third poly-silicon film; patterning the first, second and third poly-silicon films and the conductive film to form a gate electrode and a capacitor electrode at one time; and depositing an interlayer insulating film on the surface of the semiconductor substrate and then flattening the interlayer insulating film by a CMP process.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.